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Pyxsi enablement for alternative rtl simulation #1213

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Pyxsi enablement for alternative rtl simulation #1213

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auphelia
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@auphelia auphelia commented Oct 11, 2024 •
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This PR adds pyxsi as new backend for rtl simulation, ultimately it will replace pyverilator in the FINN compiler and enable more simulation capabilities, like the simulation of Vivado IP.

maltanar and others added 30 commits August 8, 2024 13:15
@maltanar
[Deps] add pyxsi fork and its deps
42cbf47
@maltanar
[Util] add util to fetch Vivado path
b6dba8a
@maltanar
[Sim] add a first draft of pyxsi-based simulation, untested
1468dbe
@maltanar
[Sim] try enabling pyxsi logging and tracing
6907167
@maltanar
[Op] experiment with enabling rtlsim with pyxsi
5a5461c
@maltanar
[Deps] update pyxsi
a50cdb6
@maltanar
[Sim] update pyxsi API to include verilog spec, assume precompiled
77680dd
@maltanar
[Deps] ensure pyxsi is compiled + set envvars for its use
1804c47
@maltanar
[Sim] remove LD_LIBRARY_PATH setting from pyxsi util, doesn't work
64e9fc1
@maltanar
[Deps] update pyxsi
d480e49
@maltanar
[AddStreams] set rtlsim_cycles for pyxsi prototyping
3560933
@maltanar
[Infra] only trigger pyxsi compile if Vivado detected
212927c
@maltanar
[Sim] move pyxsiutils to own repo, update deps, fix entrypoint chk
4fd5610
@maltanar
[pyxsi] trialling RPC server as LD_LIBRARY_PATH workaround
6e4d085
@maltanar
[Infra] remove global LD_LIBRARY_PATH setting from entrypoint
4558314
@maltanar
[pyxsi] add license text to rpcserver&client
aff109f
@maltanar
[Infra] start pyxsi rpc server in entrypoint
39ac22e
@maltanar
[Deps] update pyxsi
396cb8a
@maltanar
[Infra] redirect pyxsi rpcserver outputs to own logfile
948b5b3
@maltanar
[pyxsi] rework RPC interface to exclude rtlsim_multi_io
159e228
@maltanar
[Infra] don't launch pyxsi RPC server on startup (will be as needed)
6250c8f
@maltanar
[pyxsi] start (and then terminate when done) one pyxsi RPC server per…
42cbe0f 
… rtlsim
@auphelia
Merge branch 'dev' into feature/pyxsi_integration
db2d9a1
@maltanar @auphelia
[rtlsim] pyxsi for node-by-node rtlsim enablement via attribute
890ce81
@maltanar @auphelia
[Deps] update pyxsi
c04a4a8
@maltanar @auphelia
[pyxsi] expose close_rtlsim() to exit cleanly
b266a8a
@auphelia
[rtlsim] call close_rtlsim() to exit cleanly from pyxsi
ab3c36f
@maltanar @auphelia
[pyxsi] redirect rpcserver out to file for visible logging
fe7a942
@maltanar @auphelia
[HLS] use subcore path only if it exists
655b904
@maltanar @auphelia
[pyxsi] slightly more reliable start procedure for RPC server
acd88e5
auphelia and others added 30 commits December 9, 2024 15:16
@auphelia
[HWCustomOp] Run linting
1abe1d9
@maltanar @auphelia
[HLS] disable HLSFPO lib usage - may impact float cppsim!
fb14363
@maltanar @auphelia
[HLS] includes have moved to under Vitis path for 2024.2, specify both
9ac4e12
@maltanar @auphelia
[Deps] update pyxsi
a7ed867
@auphelia
[Tests] Re-enable stitched ip rtlsim tests for MVAUs
0634323
@auphelia
[Tests] Add vitis path to compilation in data packing tests
afda943
@maltanar @auphelia
[FIFO] call get_simkernel_so for xsicpp FIFO sizing too
6522c49
@auphelia
Merge branch 'dev' into feature/pyxsi_integration
0e7dfd3
@auphelia
[HWCustomOp] Remove unused function for characterization based fifo s…
55a3ff3 
…izing
@maltanar
[Deps] update pyxsi
6abbc53
@maltanar
[FIFO] lay groundwork for 2x-clkd xsicpp FIFO sizing
7b3e13a
@maltanar
[FIFO] check for 2x clocked stitched-IP for xsicpp fifosim
f997dd8
@maltanar
[FIFO] handle clk2x key not existing in vivado_stitch_ifnames
faa5d51
@maltanar
[FIFO] support multiple I/O streams for xsicpp fifosim
6c896e4
@maltanar
[RTLMVU] FORCE_BEHAVIORAL=0 for synth again (came from cherry picking)
ec36907
@maltanar
[XSICPP] report latency correctly
1868a11
@maltanar
[XSICPP] typo fix
407e00f
@maltanar
[XSICPP] assert timeout
5003647
@maltanar
[XSICPP] typo fix
8e7311a
@auphelia
[Util] Set default liveness threshold to 1M
946ed82
@maltanar
[XSICPP] settable liveness threshold & get from latency est for FIFO …
967e5a1 
…sizing
@maltanar
[HWCustomOp] bring back characterization with pyxsi + postclk hook
f99c5ca
@maltanar
[XSICPP] add input rate limit support
87bf4b5
@maltanar
[FIFO] wire up input rate limit support in XSICPP FIFO sizing
aa420e9
@maltanar
[Build] add cfg options for input throttling and FIFO sim trace
0bb9f1d
@maltanar
[FIFO,XSICPP] switch from rate limit to throttle cycles spec
47641a1
@auphelia
Merge branch 'dev' into feature/pyxsi_integration
cf08bc0
@auphelia
[Deps] Update pyxsi
31dc2dc
@auphelia
Merge branch 'feature/pyxsi_integration' of https://github.com/Xilinx…
0f0fbea 
…/finn into feature/pyxsi_integration
@auphelia
[Docker/CI] Add pytest-forked to dependencies and update Jenkins comm…
99aa799 
…ands
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@auphelia @maltanar @STFleming @alexhornburg-xlnx @preusser